A new SONOS flash memory device with recess channel and side-gate was proposed and designed in terms of recess depth, doping profile, and side-gate length for sub-40nm flash memory technology. The key features of the devices were characterized through 3-dimensional device simulation. This cell structure can store 2 or more bits of data in a cell when it is applied to NOR flash memory. It was shown that channel doping profile is very important depending on NOR or NAND applications. In NOR flash memory application, the localized channel doping under the source/drain junction is very important in designing threshold voltage (V_th) and suppression of drain induced barrier lowering (DIBL). In our work, this cell structure is studied not only for NAND flash memory application but also for NOR flash application. The device design was performed in terms of electrical characteristics (V_th, DIBL and SS) by considering device structure and doping profile of the cell.