IEICE Transactions on Electronics
Online ISSN : 1745-1353
Print ISSN : 0916-8524
Special Section on Microelectronic Test Structures (ICMTS2007)
A Large-Scale, Flip-Flop RAM Imitating a Logic LSI for Fast Development of Process Technology
Masako FUJII, Koji NII, Hiroshi MAKINO, Shigeki OHBAYASHI, Motoshige IGARASHI, Takeshi KAWAMURA, Miho YOKOTA, Nobuhiro TSUDA, Tomoaki YOSHIZAWA, Toshikazu TSUTSUI, Naohiko TAKESHITA, Naofumi MURATA, Tomohiro TANAKA, Takanari FUJIWARA, Kyoko ASAHINA, Masakazu OKADA, Kazuo TOMITA, Masahiko TAKEUCHI, Shigehisa YAMAMOTO, Hiromitsu SUGIMOTO, Hirofumi SHINOHARA
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Keywords: large-scale integration, logic circuit fault diagnosis, SRAM, yield optimization
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2008 Volume E91.C Issue 8 Pages 1338-1347

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Abstract

We propose a new large-scale logic test element group (TEG), called a flip-flop RAM (FF-RAM), to improve the total process quality before and during initial mass production. It is designed to be as convenient as an SRAM for measurement and to imitate a logic LSI. We implemented a 10 Mgates FF-RAM using our 65-nm CMOS process. The FF-RAM enables us to make fail-bit maps (FBM) of logic cells because of its cell array structure as an SRAM. An FF-RAM has an additional structure to detect the open and short failure of upper metal layers. The test results show that it can detect failure locations and layers effortlessly using FBMs. We measured and analyzed it for both the cell arrays and the upper metal layers. Their results provided many important clues to improve our processes. We also measured the neutron-induced soft error rate (SER) of FF-RAM, which is becoming a serious problem as transistors become smaller. We compared the results of the neutron-induced soft error rate to those of previous generations: 180nm, 130nm, and 90nm. Because of this TEG, we can considerably shorten the development period for advanced CMOS technology.

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© 2008 The Institute of Electronics, Information and Communication Engineers
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