Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor

Takeshi KUMAKI; Masakatsu ISHIZAKI; Tetsushi KOIDE; Hans Jürgen MATTAUSCH; Yasuto KURODA; Takayuki GYOHTEN; Hideyuki NODA; Katsumi DOSAKA; Kazutami ARIMOTO; Kazunori SAITO

doi:10.1093/ietele/e91-c.9.1409

Special Section on Advanced Processors Based on Novel Concepts in Computation

Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor

Takeshi KUMAKI, Masakatsu ISHIZAKI, Tetsushi KOIDE, Hans Jürgen MATTAUSCH, Yasuto KURODA, Takayuki GYOHTEN, Hideyuki NODA, Katsumi DOSAKA, Kazutami ARIMOTO, Kazunori SAITO

Author information

Takeshi KUMAKI
Research Institute for Nanodevice and Bio Systems, Hiroshima University
The Institute of Electronics, Information and Communication Engineers
Masakatsu ISHIZAKI
Research Institute for Nanodevice and Bio Systems, Hiroshima University
The Institute of Electronics, Information and Communication Engineers
Tetsushi KOIDE
Research Institute for Nanodevice and Bio Systems, Hiroshima University
The Institute of Electronics, Information and Communication Engineers
Hans Jürgen MATTAUSCH
Research Institute for Nanodevice and Bio Systems, Hiroshima University
The Institute of Electronics, Information and Communication Engineers
Yasuto KURODA
Network Memory Design Dept., System Solution Business Unit 4, System Solution Business Group, Renesas Technology Co.
Takayuki GYOHTEN
System Core Technology Div. System Solution Business Group, Renesas Technology Co.
Hideyuki NODA
System Core Technology Div. System Solution Business Group, Renesas Technology Co.
The Institute of Electronics, Information and Communication Engineers
Katsumi DOSAKA
System Core Technology Div. System Solution Business Group, Renesas Technology Co.
The Institute of Electronics, Information and Communication Engineers
Kazutami ARIMOTO
System Core Technology Div. System Solution Business Group, Renesas Technology Co.
The Institute of Electronics, Information and Communication Engineers
Kazunori SAITO
System Core Technology Div. System Solution Business Group, Renesas Technology Co.

Keywords: content addressable memory, CAM, matrix-processing architecture, SIMD, bit-serial and word-parallel, table-lookup coding, DCT, Huffman coding, JPEG

JOURNAL RESTRICTED ACCESS

2008 Volume E91.C Issue 9 Pages 1409-1418

DOI https://doi.org/10.1093/ietele/e91-c.9.1409

Details

Abstract

This paper presents an integration architecture of content addressable memory (CAM) and a massive-parallel memory-embedded SIMD matrix for constructing a versatile multimedia processor. The massive-parallel memory-embedded SIMD matrix has 2,048 2-bit processing elements, which are connected by a flexible switching network, and supports 2-bit 2,048-way bit-serial and word-parallel operations with a single command. The SIMD matrix architecture is verified to be a better way for processing the repeated arithmetic operation types in multimedia applications. The proposed architecture, reported in this paper, exploits in addition CAM technology and enables therefore fast pipelined table-lookup coding operations. Since both arithmetic and table-lookup operations execute extremely fast, the proposed novel architecture can realize consequently efficient and versatile multimedia data processing. Evaluation results of the proposed CAM-enhanced massive-parallel SIMD matrix processor for the example of the frequently used JPEG image-compression application show that the necessary clock cycle number can be reduced by 86% in comparison to a conventional mobile DSP architecture. The determined performances in Mpixel/mm² are factors 3.3 and 4.4 better than with a CAM-less massive-parallel memory-embedded SIMD matrix processor and a conventional mobile DSP, respectively.

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