IEICE Trans - Low-Voltage, Low-Distortion and Rail-to-Rail CMOS Sample and Hold Circuit

Low-Voltage, Low-Distortion and Rail-to-Rail CMOS Sample and Hold Circuit

Koichi TANNO
Kiminobu SATO
Hisashi TANAKA
Okihiko ISHIZUKA

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Vol.E88-A No.10 pp.2696-2698
Publication Date: 2005/10/01
Online ISSN:
DOI: 10.1093/ietfec/e88-a.10.2696
Print ISSN: 0916-8508
Type of Manuscript: Special Section LETTER (Special Section on Nonlinear Theory and its Applications)
Category:
Keyword:
sample hold circuit, low-voltage circuits, boost circuits, MOS analog integrated circuits, analog circuits,

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Summary:
In this letter, we propose a sample and hold circuit (S/H circuit) with the clock boost technique and the input signal tracking technique. The proposed circuit block generates the clock with the amplitude of V_DD + v_in, and the clock is used to control the MOS switch. By applying this circuit to a S/H circuit, we can deal with the rail-to-rail signal with maintaining low distortion. Furthermore, the hold error caused by the charge injection and the clock feedthrough can be also reduced by using the dummy switch. The Star-HSPICE simulation results are reported in this letter.

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