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A Low Latency Asynchronous FIFO Combining a Wave Pipeline with a Handshake Scheme Jeong-Gun LEE Suk-Jin KIM Jeong-A LEE Kiseon KIM Publication IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Vol.E88-A No.4 pp.1031-1037 Publication Date: 2005/04/01 Online ISSN: DOI: 10.1093/ietfec/e88-a.4.1031 Print ISSN: 0916-8508 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: asynchronous FIFO, wave pipeline, linear structure, forward latency, throughput, Full Text: PDF(1006.3KB)>>
Summary: This paper presents a new asynchronous FIFO design to reduce forward latency in a linear structure. The operation mode for each cell can be reconfigured dynamically as either of the two schemes, wave pipelining or handshaking, according to the data flow in the FIFO. The adoption of wave pipelining to the conventional self-timed FIFO can reduce the overhead of the handshaking as well as latching control in each stage. Initial pre-layout simulations indicate about two times of improvement on latency performance over a state-of-art asynchronous FIFO, while retaining its throughput. | ||||||||||
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