Summary
|
For Full-Text PDF, please login, if you are a member of IEICE, or go to Pay Per View on menu list, if you are a nonmember of IEICE. |
|
A 15-bit 10-Msample/s Pipelined A/D Converter Based on Incomplete Settling Principle Shuaiqi WANG Fule LI Yasuaki INOUE Publication IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Vol.E89-A No.10 pp.2732-2739 Publication Date: 2006/10/01 Online ISSN: 1745-1337 DOI: 10.1093/ietfec/e89-a.10.2732 Print ISSN: 0916-8508 Type of Manuscript: Special Section PAPER (Special Section on Nonlinear Theory and its Applications) Category: Modelling, Systems and Simulation Keyword: A/D conversion, pipelined, incomplete settling, low power dissipation, Full Text: PDF(780.6KB)>>
Summary: This paper proposes a 15-bit 10-MS/s pipelined ADC based on the incomplete settling principle. The traditional complete settling stage is improved to the incomplete settling structure through dividing the sampling clock of the traditional stage into two parts for discharging the sampling and feedback capacitors and completing the sampling, respectively. The proposed ADC verifies the correction and validity of optimizing ADCs' conversion speed without additional power consumption through the incomplete settling. This ADC employs scaling-down scheme to achieve low power dissipation and utilizes full-differential structure, bottom-plate-sampling, and capacitor-sharing techniques as well as bit-by-bit digital self-calibration to increase the ADC's linearity. It is processed in 0.18 µm 1P6M CMOS mixed-mode technology. Simulation results show that 82 dB SNDR and 87 dB SFDR are obtained at the sampling rate of 10 MHz with the input sine frequency of 100 kHz and the whole static power dissipation is 21.94 mW. | ||||||||||
| ||||||||||
