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Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule Kazunori SHIMIZU Tatsuyuki ISHIKAWA Nozomu TOGAWA Takeshi IKENAGA Satoshi GOTO Publication IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Vol.E89-A No.12 pp.3602-3612 Publication Date: 2006/12/01 Online ISSN: 1745-1337 DOI: 10.1093/ietfec/e89-a.12.3602 Print ISSN: 0916-8508 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: VLSI Architecture Keyword: low-density parity-check codes, parallel LDPC decoder architecture, message-passing algorithm, FIFO-based buffering, Full Text: PDF(1017.1KB)>>
Summary: In this paper, we propose a power-efficient LDPC decoder architecture based on an accelerated message-passing schedule. The proposed decoder architecture is characterized as follows: (i) Partitioning a pipelined operation not to read and write intermediate messages simultaneously enables the accelerated message-passing schedule to be implemented with single-port SRAMs. (ii) FIFO-based buffering reduces the number of SRAM banks and words of the LDPC decoder based on the accelerated message-passing schedule. The proposed LDPC decoder keeps a single message for each non-zero bit in a parity check matrix as well as a classical schedule while achieving the accelerated message-passing schedule. Implementation results in 0.18 [µm] CMOS technology show that the proposed decoder architecture reduces an area of the LDPC decoder by 43% and a power dissipation by 29% compared to the conventional architecture based on the accelerated message-passing schedule. | ||||||||||
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