IEICE Trans - Modeling the Influence of Input-to-Output Coupling Capacitance on CMOS Inverter Delay

Modeling the Influence of Input-to-Output Coupling Capacitance on CMOS Inverter Delay

Zhangcai HUANG
Atsushi KUROKAWA
Yun YANG
Hong YU
Yasuaki INOUE

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Vol.E89-A No.4 pp.840-846
Publication Date: 2006/04/01
Online ISSN: 1745-1337
DOI: 10.1093/ietfec/e89-a.4.840
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Category:
Keyword:
CMOS inverter, overshooting effect, deep submicron, timing analysis,

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Summary:
The modeling of gate delays has always been one of the most difficult and market-sensitive works. In submicron designs, the second-order effects such as the input-to-output coupling capacitance have a significant influence on gate delay as shown in this paper. However, the accurate analysis of the input-to-output coupling capacitance effect has not been presented in previous research. In this paper, an analytical model for the influence of the input-to-output coupling capacitance on CMOS inverter delay is proposed, in which a novel algorithm for computing overshooting time is given. Experimental results show good agreement with Spice simulations.

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