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Implementations of Low-Cost Hardware Sharing Architectures for Fast 8  8 and 44 Integer Transforms in H.264/AVCChih-Peng FAN Yu-Lian LIN Publication IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Vol.E90-A No.2 pp.511-516 Publication Date: 2007/02/01 Online ISSN: 1745-1337 DOI: 10.1093/ietfec/e90-a.2.511 Print ISSN: 0916-8508 Type of Manuscript: LETTER Category: Digital Signal Processing Keyword: fast integer transform, hardware share, H.264/AVC, Full Text: PDF(442.8KB)>>
Summary: In this paper, novel hardware sharing architectures are proposed for realizations of fast 4 4 and 88 forward/inverse integer transforms in H.264/AVC applications. Based on matrix factorizations, the cost-effective architectures for fast one-dimensional (1-D) 44 and 88 forward/inverse integer transforms can be derived through the Kronecker and direct sum operations. By applying the concept of hardware sharing, the proposed hardware schemes for fast integer transforms need a smaller number of shifters and adders than the direct realization architecture, where the direct architecture just implements the individual 44 and individual 88 integer transforms independently. With low hardware cost and regular modularity, the proposed hardware sharing architectures can process up to 125 MHz with the cost-effective area and are suitable for VLSI implementations to accomplish the H.264/AVC signal processing. | ||||||||||
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