IEICE Trans - Zero-Skew Driven Buffered RLC Clock Tree Construction

Zero-Skew Driven Buffered RLC Clock Tree Construction

Jan-Ou WU
Chia-Chun TSAI
Chung-Chieh KUO
Trong-Yen LEE

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Vol.E90-A No.3 pp.651-658
Publication Date: 2007/03/01
Online ISSN: 1745-1337
DOI: 10.1093/ietfec/e90-a.3.651
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
Keyword:
clock tree, upward propagation, buffer insertion, zero skew, SoC,

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Summary:
In nature an unbalanced clock tree exists in a SoC because the clock sinks of IPs have distinct input capacitive loads and internal delays. The construction of a bottom-up RLC clock tree with minimal clock delay and zero skew is crucial to ensure good SoC performance. This study proves that an RLC clock tree construction always has no zero skew owing to skew upward propagation. Specifically, this study proposes the insertion of two unit-size buffers associated with the binary search for a tapping point into each pair of subtrees to interrupt the non-zero skew upward propagation. This technique enables reliable construction of a buffered RLC clock tree with zero skew. The effectiveness of the proposed approach is demonstrated by assessing benchmarks.

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