IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Online ISSN : 1745-1337
Print ISSN : 0916-8508
Special Section on VLSI Design and CAD Algorithms
A Parallel Method to Extract Critical Areas of Net Pairs for Diagnosing Bridge Faults
Keiichi SUEMITSUToshiaki ITOToshiki KANAMOTOMasayuki TERAISatoshi KOTANIShigeo SAWADA
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2008 Volume E91.A Issue 12 Pages 3524-3530

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Abstract

This paper proposes a new parallel method of producing the adjacent net pair list from the LSI layouts, which is run on workstations connected with the network. The pair list contains pairs of adjacent nets and the probability of a bridging fault between them, and is used in fault diagnosis of LSIs. The proposed method partitions into regions each mask layer of the LSI layout, produces a pair list corresponding to each region in parallel and merges them into the entire pair list. It yields the accurate results, because it considers the faults between two wires containing different adjacent regions. The experimental results show that the proposed method has greatly reduced the processing time from more than 60hrs. to 3hrs. in case of 42M-gate LSIs.

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© 2008 The Institute of Electronics, Information and Communication Engineers
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