IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Online ISSN : 1745-1337
Print ISSN : 0916-8508
Regular Section
Scalable and Systolic Montgomery Multipliers over GF (2m)
Chin-Chin CHENChiou-Yng LEEErl-Huei LU
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2008 Volume E91.A Issue 7 Pages 1763-1771

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Abstract

This work presents a novel scalable and systolic Montgomery's algorithm in GF (2m). The proposed algorithm is based on the Toeplitz matrix-vector representation, which obtains the scalable and systolic Montgomery multiplier in a flexible manner, and can adapt to the required precision. Analytical results indicate that the proposed multiplier over the generic field of GF (2m) has a latency of d+n(2n+1), where n=[m/d], and d denotes the selected digital size. The latency is reduced to d+n(n+1) clock cycles when the field is constructed from generalized equally-spaced polynomials. Since the selected digital size is d≥5 bits, the proposed architectures have lower time-space complexity than traditional digit-serial multipliers. Moreover, the proposed architectures have regularity, modularity and local interconnect ability, making them very suitable for VLSI implementation.

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© 2008 The Institute of Electronics, Information and Communication Engineers
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