Logic-Level Analysis of Fault Attacks and a Cost-Effective Countermeasure Design

Masahiro KAMINAGA; Takashi WATANABE; Takashi ENDO; Toshio OKOCHI

doi:10.1093/ietfec/e91-a.7.1816

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Online ISSN : 1745-1337
Print ISSN : 0916-8508

Regular Section

Logic-Level Analysis of Fault Attacks and a Cost-Effective Countermeasure Design

Masahiro KAMINAGA, Takashi WATANABE, Takashi ENDO, Toshio OKOCHI

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Keywords: fault attack, hardware security

JOURNAL RESTRICTED ACCESS

2008 Volume E91.A Issue 7 Pages 1816-1819

DOI https://doi.org/10.1093/ietfec/e91-a.7.1816

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Abstract

This article analyzes the internal mechanism of fault attacks on microcontrollers and proposes a cost-effective hardware and software countermeasure design policy. Reliable branch operations are essential to DFA-resistant hardware. Our method is based on a logical fault attack simulation to find the minimum set of signals that contribute to faults in the branch operations and is also based on applying partially redundant logic.

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