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Failure Trace Analysis of Timed Circuits for Automatic Timing Constraints Derivation Tomoya KITAI Tomohiro YONEDA Chris MYERS Publication IEICE TRANSACTIONS on Information and Systems Vol.E88-D No.11 pp.2555-2564 Publication Date: 2005/11/01 Online ISSN: DOI: 10.1093/ietisy/e88-d.11.2555 Print ISSN: 0916-8532 Type of Manuscript: PAPER Category: Dependable Computing Keyword: trace theoretic verification, failure analysis, timed circuits, timing constraints, Full Text: PDF(815.5KB)>>
Summary: This work proposes a technique to automatically obtain timing constraints for a given timed circuit to operate correctly. A designated set of delay parameters of a circuit are first set to sufficiently large bounds, and verification runs followed by failure analysis are repeated. Each verification run performs timed state space enumeration under the given delay bounds, and produces a failure trace if it exists. The failure trace is analyzed, and sufficient timing constraints to prevent the failure are obtained. Then, the delay bounds are tightened according to the timing constraints by using an ILP (Integer Linear Programming) solver. This process terminates when either some delay bounds under which no failure is detected are found or no new delay bounds to prevent the failures can be obtained. The experimental results using a naive implementation show that the proposed method can efficiently handle asynchronous benchmark circuits and nontrivial GasP circuits. | ||||||||||
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