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Boundary Scan Test Scheme for IP Core Identification via Watermarking Yu-Cheng FAN Hen-Wai TSAO Publication IEICE TRANSACTIONS on Information and Systems Vol.E88-D No.7 pp.1397-1400 Publication Date: 2005/07/01 Online ISSN: DOI: 10.1093/ietisy/e88-d.7.1397 Print ISSN: 0916-8532 Type of Manuscript: Special Section LETTER (Special Section on Recent Advances in Circuits and Systems--Part 1) Category: Programmable Logic, VLSI, CAD and Layout Keyword: boundary scan test scheme (BSTS), intellectual property (IP) identification, system on a chip (SOC), VLSI design, watermarking, Full Text: PDF(825.5KB)>>
Summary: This paper proposes a novel boundary scan test scheme for intellectual property (IP) core identification via watermarking. The core concept is embedding a watermark identification circuit (WIC) and a test circuit into the IP core at the behavior design level. The procedure depends on current IP-based design flow. This scheme can detect the identification of the IP provider without the need to examine the microphotograph after the chip has been manufactured and packaged. This scheme can successfully survive synthesis, placement, and routing and identify the IP core at various design levels. Experimental results have demonstrated that the proposed approach has the potential to solve the IP identification problem. | ||||||||||
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