Summary
|
For Full-Text PDF, please login, if you are a member of IEICE, or go to Pay Per View on menu list, if you are a nonmember of IEICE. |
|
Low Latency Four-Flop Synchronizer with the Handshake Interface Suk-Jin KIM Jeong-Gun LEE Kiseon KIM Publication IEICE TRANSACTIONS on Information and Systems Vol.E88-D No.7 pp.1460-1463 Publication Date: 2005/07/01 Online ISSN: DOI: 10.1093/ietisy/e88-d.7.1460 Print ISSN: 0916-8532 Type of Manuscript: Special Section LETTER (Special Section on Recent Advances in Circuits and Systems--Part 1) Category: Communications and Wireless Systems Keyword: synchronizer, two-flop, clock domain, SoC, Full Text: PDF(445.9KB)>>
Summary: This letter presents a synchronizer and its handshake interface for bridging clock domains in SoC. The proposed scheme uses a double two-flop synchronizer operated at different clock edges respectively, based on a two-phase handshake protocol. Performance analysis shows that the proposed design reduces latency up to a clock cycle, while retaining its safety to a tolerable level. | ||||||||||
| ||||||||||
