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Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits Denduang PRADUBSUWUN Tomohiro YONEDA Chris MYERS Publication IEICE TRANSACTIONS on Information and Systems Vol.E88-D No.7 pp.1646-1661 Publication Date: 2005/07/01 Online ISSN: DOI: 10.1093/ietisy/e88-d.7.1646 Print ISSN: 0916-8532 Type of Manuscript: PAPER Category: Dependable Computing Keyword: timed trace theory, timed circuits, formal verification, safety/timing failures, Full Text: PDF(1MB)>>
Summary: This paper proposes a partial order reduction algorithm for timed trace theoretic verification in order to detect both safety failures and timing failures of timed circuits efficiently. This algorithm is based on the framework of timed trace theoretic verification according to the original untimed trace theory. Consequently, its conformance checking supports hierarchical structure when verifying timed circuits. Experimenting with the STARI and DME circuits, the proposed approach shows its effectiveness. | ||||||||||
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