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Concurrent Symbol Processing Capable VLSI Architecture for Bit Plane Coder of JPEG2000 Amit Kumar GUPTA Saeid NOOSHABADI David TAUBMAN Publication IEICE TRANSACTIONS on Information and Systems Vol.E88-D No.8 pp.1878-1884 Publication Date: 2005/08/01 Online ISSN: DOI: 10.1093/ietisy/e88-d.8.1878 Print ISSN: 0916-8532 Type of Manuscript: Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 2) Category: Image Processing and Multimedia Systems Keyword: JPEG2000, concurrent symbol processing, bit plane coder, VLSI architecture, Full Text: PDF(648.3KB)>>
Summary: JPEG2000 image compression standard is designed to cater the needs of a large span of applications including numerous consumer products. However, its use is restricted due to the high hardware cost involved in its implementation. Bit Plane Coder (BPC) is the main resource intensive component of JPEG2000. Its throughput plays a key role in deciding the overall throughput of a JPEG2000 encoder. In this paper we present the algorithm and parallel pipelined VLSI architecture for BPC which processes a complete stripe-column concurrently during every pass. The hardware requirements and the critical path delay of the proposed technique are compared with the existing solutions. The experimental results show that the proposed architecture has 2.6 times greater throughput than existing architectures, with a comparatively small increase in hardware cost. | ||||||||||
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