Publication IEICE TRANSACTIONS on Information and SystemsVol.E89-DNo.1pp.354-357 Publication Date: 2006/01/01 Online ISSN: 1745-1361 DOI: 10.1093/ietisy/e89-d.1.354 Print ISSN: 0916-8532 Type of Manuscript: LETTER Category: Dependable Computing Keyword: deterministic logic BIST, embedded core testing,
Full Text: PDF(587.3KB)>>
Summary: In this paper, we propose a new clustered reconfigurable interconnect network (CRIN) BIST that can improve the embedding probabilities of random-pattern-resistant-patterns. A simulated annealing based algorithm that maximizes the embedding probabilities of scan test cubes has been developed to reorder scan cells. Experimental results demonstrate that the proposed CRIN BIST technique reduces test time by 35% and the storage requirement by 39% in comparison with previous work.