Publication IEICE TRANSACTIONS on Information and SystemsVol.E89-DNo.4pp.1490-1497 Publication Date: 2006/04/01 Online ISSN: 1745-1361 DOI: 10.1093/ietisy/e89-d.4.1490 Print ISSN: 0916-8532 Type of Manuscript: PAPER Category: Dependable Computing Keyword: SoC, test scheduling, wrapper, design for test, memory BIST,
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Summary: With the increasing demand for SoCs to include rich functionality, SoCs are being designed with hundreds of small memories with different sizes and frequencies. If memory BIST logics were individually added to these various memories, the area overhead would be very high. To reduce the overhead, memory BIST logic must therefore be shared. This paper proposes a memory-grouping method for memory BIST logic sharing. A memory-grouping problem is formulated and an algorithm to solve the problem is proposed. Experimental results show that the proposed method reduced the area of the memory BIST wrapper by up to 40.55%. The results also show that the ability to select from two types of connection methods produced a greater reduction in area than using a single connection method.