IEICE Trans - Hardware Implementation of an Inverse Function Delayed Neural Network Using Stochastic Logic

Hardware Implementation of an Inverse Function Delayed Neural Network Using Stochastic Logic

Hongge LI
Yoshihiro HAYAKAWA
Shigeo SATO
Koji NAKAJIMA

Publication
IEICE TRANSACTIONS on Information and Systems Vol.E89-D No.9 pp.2572-2578
Publication Date: 2006/09/01
Online ISSN: 1745-1361
DOI: 10.1093/ietisy/e89-d.9.2572
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Biocybernetics, Neurocomputing
Keyword:
inverse function delayed model, associative memory, field programmable gate array (FPGA), stochastic logic,

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Summary:
In this paper, the authors present a new digital circuit of neuron hardware using a field programmable gate array (FPGA). A new Inverse function Delayed (ID) neuron model is implemented. The Inverse function Delayed model, which includes the BVP model, has superior associative properties thanks to negative resistance. An associative memory based on the ID model with self-connections has possibilities of improving its basin sizes and memory capacity. In order to decrease circuit area, we employ stochastic logic. The proposed neuron circuit completes the stimulus response output, and its retrieval property with negative resistance is superior to a conventional nonlinear model in basin size of an associative memory.

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