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Latency-Aware Bus Arbitration for Real-Time Embedded Systems Minje JUN Kwanhu BANG Hyuk-Jun LEE Eui-Young CHUNG Publication IEICE TRANSACTIONS on Information and Systems Vol.E90-D No.3 pp.676-679 Publication Date: 2007/03/01 Online ISSN: 1745-1361 DOI: 10.1093/ietisy/e90-d.3.676 Print ISSN: 0916-8532 Type of Manuscript: LETTER Category: VLSI Systems Keyword: latency, arbiter, QoS, performance, bus, slack, Full Text: PDF(297.4KB)>>
Summary: We present a latency-aware bus arbitration scheme for real-time embedded systems. Only a few works have addressed the quality of service (QoS) issue for traditional busses or interconnection network. They mostly aimed at minimizing the latencies of several master blocks, resulting in decreasing overall bandwidth and/or increasing the latencies of other master blocks. In our method, the optimization goal is different in that the latency of a master should be as close as a given latency constraint. This is achieved by introducing the concept of "slack". In this method, masters effectively share the given communication architecture so that they all observe expected latencies and the degradation of overall bandwidth is marginal. The experimental results show that our method greatly reduces the number of constraint violations compared to other conventional arbitration schemes while minimizing the bandwidth degradation. | ||||||||||
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