Summary
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A VLSI Design of a Pipelining and Area-Efficient Reed-Solomon Decoder Wei-min WANG Du-yan BI Xing-min DU Lin-hua MA Publication IEICE TRANSACTIONS on Information and Systems Vol.E90-D No.8 pp.1301-1303 Publication Date: 2007/08/01 Online ISSN: 1745-1361 DOI: 10.1093/ietisy/e90-d.8.1301 Print ISSN: 0916-8532 Type of Manuscript: LETTER Category: VLSI Systems Keyword: Reed-Solomon code, modified Euclid algorithm, Chien search and Forney algorithm, critical path, Full Text: PDF(94.3KB)>>
Summary: A novel high-speed and area-efficient Reed-Solomon decoder is proposed, which employs pipelining architecture of minimized modified Euclid (ME) algorithm. The logic synthesis and simulation results of its VLSI implementation show that it not only can operate at a higher clock frequency, but also consumes fewer hardware resources. | ||||||||||
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