Summary
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A Novel ATPG Method for Capture Power Reduction during Scan Testing Xiaoqing WEN Seiji KAJIHARA Kohei MIYASE Tatsuya SUZUKI Kewal K. SALUJA Laung-Terng WANG Kozo KINOSHITA Publication IEICE TRANSACTIONS on Information and Systems Vol.E90-D No.9 pp.1398-1405 Publication Date: 2007/09/01 Online ISSN: 1745-1361 DOI: 10.1093/ietisy/e90-d.9.1398 Print ISSN: 0916-8532 Type of Manuscript: PAPER Category: Dependable Computing Keyword: scan testing, capture power, X-bit, IR-drop, Full Text: PDF(1.6MB)>>
Summary: High power dissipation can occur when the response to a test vector is captured by flip-flops in scan testing, resulting in excessive IR drop, which may cause significant capture-induced yield loss in the DSM era. This paper addresses this serious problem with a novel test generation method, featuring a unique algorithm that deterministically generates test cubes not only for fault detection but also for capture power reduction. Compared with previous methods that passively conduct X-filling for unspecified bits in test cubes generated only for fault detection, the new method achieves more capture power reduction with less test set inflation. Experimental results show its effectiveness. | ||||||||||
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