Mechanical stress, crystal defects, and metal contamination in thinned silicon substrates with and without intrinsic gettering (IG) zone have been investigated for three-dimensional (3D) integration. The remnant stress existing after wafer thinning was evaluated using angle-(5deg) polished silicon wafers by micro-Raman spectroscopy (muRS). The metal contamination in the thinned silicon substrates has been evaluated by a capacitance-time (C-t) measurement method using MOS capacitors in which the thinned silicon substrates were diffused with metallic impurities such as Cu and Au used for through-silicon via (TSV) and metal microbump in 3D LSI.