3D integration opens up entirely new perspectives in chip development, such as integration of different technologies in a stack with smaller form factor as with classical board design. It enables also the partitioning of large SOC designs into a stack with two or more dies. If the resulting 3D-System is optimized, its costs can be smaller than the costs for the manufacturing of the corresponding 2D-System. In this paper a new layout dependent synthesis method for manufacturing costs optimized 3D integrated systems is introduced. As its major part a 3D synthesis optimization method algorithm which used layout information from a floorplanner is presented. The flow was tested on a VLIW processor design, which demonstrates a cost reduction by 3D implementation.