Three dimensional ICs are expected to bring about a new generation of integration by allowing for a smaller footprint, faster operation, and lower energy consumption. Manufacturing defects in through-silicon via (TSV) and disconnection defects among tiers are concerns in this new technology. To prevent yield loss from these defects, confirming known-good-die (KGD) and known-good-stacks (KGS) by test is a critical issue. In this paper, embedded test circuitry is proposed to guarantee KGD and KGS by measuring noise on the silicon substrate. The proposed test circuit consists of simple circuitry and potentially can test multiple TSVs with just a single channel of test circuitry. Testing by using substrate noise measurements does not require direct electrical connections. Hence, the proposed test structure does not invade the original circuit design. An analytical model is created to indicate effectivity of the test structure. Analytical result shows a single channel of test circuitry can test 72 TSVs of the same pitch, such as would be encountered in Wide-I/O. Use of the test structure both during initial calibration and then during actual product use are discussed.