3D VLSI technology based on CoolCube^™ process offers ultra-high density of integration with up to 10⁸ 3D Vias (3D-V) per mm² offering gate level 3D integration capability. For process stability and wide range of temperature compliancy, Intermediate Back End of Line (IBEOL) is targeted to be made with Tungsten lines in a SiO₂ (k=3.9) dielectric, increasing equivalent resistivity by 6 and capacitance by 1.6 compared to standard Back End of Line (BEOL) (copper lines in low k dielectrics). In this study we propose to study impact in Performance, Power and Area (PPA) using W/SiO₂ compared to Cu/low-k IBEOL. Results show area gain up to 60.9% and performance gain up to 21.7% for 3D cases comparing to 2D using 28 nm FDSOI technology. Using W/SiO₂ shows limited impact on performance with maximal 1.93% degradation comparing to Cu/low-k IBEOL.