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Consideration of microbump layout for reduction of local bending stress due to CTE Mismatch in 3D IC | IEEE Conference Publication | IEEE Xplore

Consideration of microbump layout for reduction of local bending stress due to CTE Mismatch in 3D IC


Abstract:

Three-dimensional IC (3D IC) has attracted much attention as a promising method to enhance IC performance. Recently, great interests in mechanical reliability are increas...Show More

Abstract:

Three-dimensional IC (3D IC) has attracted much attention as a promising method to enhance IC performance. Recently, great interests in mechanical reliability are increasing among 3D IC researchers for production of 3D IC. Conventional 3D ICs consist of vertically stacked several thin IC chips those are electrically connected with lots of through-Si vias (TSVs) and metal microbumps. Metal microbumps are surrounded by organic adhesive called underfill material. In general, coefficient of thermal expansion (CTE) of the underfill material is larger than that of metal microbumps. This CTE difference induces local bending stress in thinned IC chips. This local bending stress would affect transistor reliability in thinned IC chips. Therefore, we should suppress the local bending stress to realize 3D IC with high reliability. In this work, we present design guideline of microbump layout which can suppress the local bending stress in 3D-stacked several thin IC chips.
Date of Conference: 31 August 2015 - 02 September 2015
Date Added to IEEE Xplore: 23 November 2015
ISBN Information:
Conference Location: Sendai, Japan

References

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