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A redundancy test-time reduction technique in 1-Mbit DRAM with a multibit test mode | IEEE Journals & Magazine | IEEE Xplore

A redundancy test-time reduction technique in 1-Mbit DRAM with a multibit test mode


Abstract:

To realize an efficient redundancy test using the multibit test (MBT) mode, a redundancy flag on a memory LSI tester and an effective redundancy technique which cooperate...Show More

First Page of the Article

Abstract:

To realize an efficient redundancy test using the multibit test (MBT) mode, a redundancy flag on a memory LSI tester and an effective redundancy technique which cooperates with the MBT mode have been introduced. This simple redundancy architecture needs only the RFLG (512 bits for the 1 M*1-bit DRAM) as a hardware option on a memory LSI tester. The program development time for the redundancy test has been shortened. Throughput improvement of six to ten times has been achieved in the actual 1-Mb DRAM redundancy test.<>
Published in: IEEE Journal of Solid-State Circuits ( Volume: 24, Issue: 1, February 1989)
Page(s): 43 - 49
Date of Publication: 06 August 2002

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First Page of the Article


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