A novel pipeline digital-to-analog converter (DAC) configuration, based on switched-capacitor techniques, is described. An n-bit D/A conversion can be implemented by cascading n+1 unit cells. The device count of the circuit increases linearly, not exponentially, with the conversion accuracy. The new configuration can be pipelined. Hence, the conversion rate can be increased without requiring a higher clock rate. An experimental 10-b DAC prototype has been fabricated using a 3- mu m CMOS process. The results show that high-speed, high-accuracy, and low-power operation can be achieved without special process or postprocess trimming.<>