Abstract:
An 8-Mb (1-Mwords*8-b) dynamic RAM which utilizes a column direction drive sense amplifier to obtain low peak current is described. The power supply peak current is about...Show MoreMetadata
Abstract:
An 8-Mb (1-Mwords*8-b) dynamic RAM which utilizes a column direction drive sense amplifier to obtain low peak current is described. The power supply peak current is about one fourth of that for conventional circuits. The chip operates at 50-MHz and is fabricated with a 0.7- mu m n-well CMOS, double-level polysilicon, single-polycide, and double-level metal technology. The memory cell is a surrounding hi-capacitance cell structure. The cell size is 1.8*3.0 mu m/sup 2/, and the chip area is 12.7*16.91 mm/sup 2/.<>
Published in: IEEE Journal of Solid-State Circuits ( Volume: 25, Issue: 1, February 1990)
DOI: 10.1109/4.50280