A 23-ns 1-Mb BiCMOS DRAM | IEEE Journals & Magazine | IEEE Xplore

A 23-ns 1-Mb BiCMOS DRAM


Abstract:

A 1-Mb BiCMOS DRAM having a 23-ns access time is described. The DRAM uses a direct sensing technique and a nonaddress-multiplexing configuration. This technique combines ...Show More

Abstract:

A 1-Mb BiCMOS DRAM having a 23-ns access time is described. The DRAM uses a direct sensing technique and a nonaddress-multiplexing configuration. This technique combines the NMOS differential circuit on each pair of data lines with a common highly sensitive bipolar circuit. The resulting chip has been verified to have high-speed characteristics while maintaining a wide operating margin and a relatively small chip size of 62.2 mm/sup 2/, in spite of a 1.3- mu m lithography level.<>
Published in: IEEE Journal of Solid-State Circuits ( Volume: 25, Issue: 5, October 1990)
Page(s): 1102 - 1111
Date of Publication: 31 October 1990

ISSN Information:


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