Abstract:
Slow input ramp effects in delay evaluation on CMOS structures are considered. Corrections of previously defined closed-form equations are proposed, allowing accurate eva...Show MoreMetadata
Abstract:
Slow input ramp effects in delay evaluation on CMOS structures are considered. Corrections of previously defined closed-form equations are proposed, allowing accurate evaluation of delays in a large range of configurations. The expressions obtained remain sufficiently manageable to be used in an automatic data-path sizing tool.<>
Published in: IEEE Journal of Solid-State Circuits ( Volume: 25, Issue: 6, December 1990)
DOI: 10.1109/4.62196
