As part of the entire readout chip, a low-power high-gain transresistance amplifier has been developed, followed by a high-speed, low-power small offset comparator and a binary delay line. The amplifier is balanced, fully differential in circuit topology, and symmetrical in layout, making it radiation tolerant and relatively insensitive to varying magnetic fields. Also, the comparator is fully symmetrical with a balanced input stage. Before irradiation (pre-rad) the transresistance amplifier has a measured differential gain of 110 mV/4 fC, an average 10/90% rise time (t/sub 10/90%/) of 20 to 50 ns depending on the bias conditions, a noise figure of 433/spl oplus/93.(C/sub t/)/sup 1.08/ (where the symbol /spl oplus/ stands for /spl radic/(()/sup 2/+()/sup 2/)) electrons (e/sup -/), and a power consumption of 750 /spl mu/W. The comparator uses bipolar transistors in the regenerative stage resulting in a small offset, a sensitivity <1.5 mV, and a power consumption of /spl ap/350 /spl mu/W at 40 MHz. The maximum pre-rad frequency at which the comparator is still functioning correctly is /spl ap/100 MHz. Pre-rad, the binary delay line has a delay of 2.1 /spl mu/s at 40 MHz and a power consumption of /spl ap/450 /spl mu/W/channel for a four-channel design. The complete readout channel-amplifier, comparator, and binary delay line-consumes /spl ap/1.5 mW. The entire readout system was implemented in the radiation-hard 0.8-/spl mu/m SOI-SIMOX BiCMOS-PJFET technology of DMILL.