Abstract:
A new method for the parallel hardware implementation of artificial neural network (ANN) using digital techniques is presented. Uniformly weighted bit-streams are used to...Show MoreMetadata
Abstract:
A new method for the parallel hardware implementation of artificial neural network (ANN) using digital techniques is presented. Uniformly weighted bit-streams are used to represent bipolar analogue signals. Operations necessary for neural network behaviour like summing, scaling and squashing have been implemented and presented. The bit- stream architecture is inherently parallel in nature and easily implemented on an field programmable gate array (FPGA) using standard hardware description language (HDL). This technique has been demonstrated using two standard pattern classifiers and a non-linear function approximator.
Published in: 2007 American Control Conference
Date of Conference: 09-13 July 2007
Date Added to IEEE Xplore: 30 July 2007
ISBN Information: