The dynamic reconfiguration of recent FPGAs offers an important step to adaptive behavior of Systems-on-Chip (SoCs). These dynamically reconfigurable systems add another degree of freedom to the design space. When a processing element gets reconfigured using one with a different architecture, heterogeneity spans the temporal dimension, too. Now, the question arises how could this type of heterogeneity be managed at run time. This paper analyzes the challenges of such an adaptive SoC. We show that many of the requirements for an FPGA-based realization are met by the SDVM, the Scalable Dataflow-driven Virtual Machine which has been successfully implemented and tested on a cluster of workstations. Focusing on run time reconfiguration, the SDVM has evolved to a virtualization layer for multicore systems based on FPGAs, now called SDVM^R. This virtualization layer allows for a transparent run time reconfiguration of the underlying hardware reducing the complexity of the system's temporal heterogeneity as seen by the application.