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Hardware requirements of communication-centric machine learning algorithms | IEEE Conference Publication | IEEE Xplore

Hardware requirements of communication-centric machine learning algorithms


Abstract:

Machine learning type neuromorphic algorithms have the potential to enable the brains behind small autonomous robots, provided these algorithms can be implemented energy ...Show More

Abstract:

Machine learning type neuromorphic algorithms have the potential to enable the brains behind small autonomous robots, provided these algorithms can be implemented energy efficiently. The implementation difficulties are mainly extremely large memory size and high memory bandwidth making Von Neumann computational model realizations inefficient. However, these algorithms are inherently error robust, which may be taken advantage of in the realizations. For example, in with low operating voltage stochastic hardware. To determine the hardware requirements for an Application Specific Integrated Circuit (ASIC) realization, an example algorithm, Hierarchical Temporal Memory (HTM), is realized here. A 64×64 HTM network with 1440 connections per elementary processing element requires 530 mm2 area, 340 Mb memory, and a 10MHz clock frequency in 65nm technology. With point-to-point connections these processing elements would have a communication radius of circa 50 elements and on-chip wideband technologies can increase the range further.
Date of Conference: 24-27 June 2013
Date Added to IEEE Xplore: 19 September 2013
Electronic ISBN:978-1-4673-6383-9
Conference Location: Turin, Italy

References

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