Abstract:
Reconfigurable devices are widely attractive for several application fields thanks to their size, rapid prototyping characteristics, flexibility and upgradability. Thanks...Show MoreMetadata
Abstract:
Reconfigurable devices are widely attractive for several application fields thanks to their size, rapid prototyping characteristics, flexibility and upgradability. Thanks to partial Reconfiguration features, FPGA becomes the golden core of the adaptive computation paradigm since they may dynamically change their functionalities based on the elaboration request. Today, adaptive computation is mainly controlled at a coarse-grain granularity while no solutions exist to act at the fine granularity level especially to reprogram the FPGA routing interconnection. The purpose of this work is to propose an embedded core able to reconfigure the routing resources without the usage of external computational units. The developed core implements a Path Finding-based algorithm able to perform the full routability of complex designs. The core has been devised minimizing the area overhead and the requested computational power by wisely selecting a suitable subset of wiring segments. The functionalities of the core have been tested on a Xilinx SRAM-based FPGAs Zynq device using three different circuit benchmarks. Experimental results demonstrated that the core is able to successfully re-route almost 95% of the selected nets without introducing a relevant delay or area overhead.
Date of Conference: 24-27 July 2017
Date Added to IEEE Xplore: 21 September 2017
ISBN Information:
Electronic ISSN: 2471-769X