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Chip to chip communications for terabit transmission rates

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B. Moore; C. Sellathamby; S. Slupsky; K. Iniewski
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Abstract:

I/O data throughput remains a bottleneck in high-speed chip to chip data communication. This paper discusses the latest technical innovations in increasing the I/O bandwi...Show More

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Abstract:

I/O data throughput remains a bottleneck in high-speed chip to chip data communication. This paper discusses the latest technical innovations in increasing the I/O bandwidth while reducing energy per transition. Both wireline techniques that include DSP processing and equalization, and wireless transmissions that include on-chip inductive and capacitive coupling are discussed and compared.
Published in: APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
Date of Conference: 30 November 2008 - 03 December 2008
Date Added to IEEE Xplore: 09 January 2009
ISBN Information:
DOI: 10.1109/APCCAS.2008.4746331
Conference Location: Macao, China
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