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Timing-constrained yield-driven redundant via insertion | IEEE Conference Publication | IEEE Xplore

Timing-constrained yield-driven redundant via insertion


Abstract:

In this paper, based on the equivalent circuit of on-track or off-track redundant via insertion and the timing delay of each net in as the timing constraint, an enhanced ...Show More

Abstract:

In this paper, based on the equivalent circuit of on-track or off-track redundant via insertion and the timing delay of each net in as the timing constraint, an enhanced timing-constrained two-phase insertion approach for yield optimization is proposed to insert on-track and off-track redundant vias. For the Poisson yield model in redundant via insertion, the experimental results show that our proposed enhanced two-phase insertion approach can further reduce 0.006% total wire length on the average with the reduction of 0.0002% chip yield to maintain 100% timing constraints for the tested benchmarks.
Date of Conference: 30 November 2008 - 03 December 2008
Date Added to IEEE Xplore: 09 January 2009
ISBN Information:
Conference Location: Macao, China

References

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