Abstract:
This paper proposes the high-performance architecture of unified inverse transform circuit for H.264/AVC high profile decoder. Four processing elements operate in paralle...Show MoreMetadata
Abstract:
This paper proposes the high-performance architecture of unified inverse transform circuit for H.264/AVC high profile decoder. Four processing elements operate in parallel to achieve the high performance. Two-stage pipeline technique is applied in each processing element. All inverse transforms required in H.264/AVC high profile decoding are covered by the proposed circuit. Our circuit consists of 29,731 gates and its maximum operation frequency is 107MHz when synthesized using 130nm standard cell library.
Date of Conference: 06-09 December 2010
Date Added to IEEE Xplore: 27 May 2011
ISBN Information: