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A small die area and high linearity 10-bit capacitive three-level DAC | IEEE Conference Publication | IEEE Xplore

A small die area and high linearity 10-bit capacitive three-level DAC


Abstract:

A 10-bit capacitive three-level digital-to-analog converter (TLDAC) is provided to reduce differential non-linearity (DNL) and integral non-linearity (INL) caused by capa...Show More

Abstract:

A 10-bit capacitive three-level digital-to-analog converter (TLDAC) is provided to reduce differential non-linearity (DNL) and integral non-linearity (INL) caused by capacitive mismatch. The simulation results of binary-weighted TLDAC show 50 % reduction in DNL and INL compared to conventional binary-weighted DAC. Furthermore an additional reference voltage source has been reduced due to the advantages of differential circuit. The proposed 10-bit differential TLDAC was implemented in 0.18 μm CMOS process and its total area is 0.081 mm2.
Date of Conference: 02-05 December 2012
Date Added to IEEE Xplore: 24 January 2013
ISBN Information:
Conference Location: Kaohsiung, Taiwan

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