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A post-processing algorithm for reducing strong error effects in NAND flash memory | IEEE Conference Publication | IEEE Xplore

A post-processing algorithm for reducing strong error effects in NAND flash memory


Abstract:

This paper introduces a novel post-processing algorithm for low-density parity-check (LDPC) codes adequate for NAND flash memory, to improve error correction capability o...Show More

Abstract:

This paper introduces a novel post-processing algorithm for low-density parity-check (LDPC) codes adequate for NAND flash memory, to improve error correction capability of a soft decision decoding by reducing strong error effects in an efficient way. In this algorithm, it can detect variable nodes of strong errors using incoming check-to-variable (c2v) messages and reduce magnitude of channel reliability of the nodes to avoid supplying large erroneous variable-to-check (v2c) messages for the check nodes. The proposed post processing algorithm with a finite precision LDPC decoding scheme is named edge-based post processing and effectively reflects time varying characteristic of NAND flash channel.
Date of Conference: 25-28 October 2016
Date Added to IEEE Xplore: 05 January 2017
ISBN Information:
Conference Location: Jeju, Korea (South)

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