Abstract:
This paper presents a new Differential Cascode Voltage Switch Logic (DCVSL) design method which combines the differential logic design style with an analog current mirror...Show MoreMetadata
Abstract:
This paper presents a new Differential Cascode Voltage Switch Logic (DCVSL) design method which combines the differential logic design style with an analog current mirror. Compared to conventional DCVSL circuits, the proposed circuits have significant performance improvements with reduced switching latency. More importantly, our proposed circuits can successfully operate with low voltage supply, which is verified by the design the basic logic gates. We provide comparison results with conventional logic gates including AND/NAND, OR/NOR and XOR/NXOR to demonstrate the advantages of using our proposed design in terms of latency, power dissipation and area. With 1V supply voltage, 4ns signal period (250MHz), the simulated PDP is 7.86aWs for AND/NAND, OR/NOR gates, and 9.84aWs for XOR/NXOR gate, that is 51.67% and 24.31% performance improvement compared to the best case of conventional circuits.
Date of Conference: 26-30 October 2018
Date Added to IEEE Xplore: 10 January 2019
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