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A GALS Design with Opposite-Phase Local Clock Assignment for Power Supply Noise Reduction | IEEE Conference Publication | IEEE Xplore

A GALS Design with Opposite-Phase Local Clock Assignment for Power Supply Noise Reduction


Abstract:

This paper presents a globally asynchronous locally synchronous (GALS) design with an "opposite-phase" local clock assignment to reduce the power supply noise. With the G...Show More

Abstract:

This paper presents a globally asynchronous locally synchronous (GALS) design with an "opposite-phase" local clock assignment to reduce the power supply noise. With the GALS design, the power supply noise can be spread over different clock frequencies or phases. By incrementally applying the opposite-phase local clock assignment to locally synchronous logics, the simultaneous switching activities can be more distributed in time. The experimental results on a GALS triple-DES crypto processor implemented in a Xilinx Spartan-6 Field Programmable Gate Array (FPGA) show that the supply noises are attenuated about 16.9 dB and 10.9 dB for the fundamental and the second harmonic, respectively.
Date of Conference: 26-30 October 2018
Date Added to IEEE Xplore: 10 January 2019
ISBN Information:
Conference Location: Chengdu, China

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