This paper presents a 12-bit 20-MS/s SAR ADC incorporating the window-switching technique. The proposed fast-binary-window DAC switching scheme can effectively remove the major capacitor-DAC transition error to improve the DAC linearity and suppress DAC switching errors to improve the SNR. To maintain a good production yield, a dual-reference capacitor-DAC is applied to have a small total capacitance. The ADC was implemented in 180nm CMOS. It consumes 1.22 mW from a 1.5-V supply. The measured peak SNDR and SFDR are 61.9 and 81 dB, respectively. The peak ENOB is 10 bits, equivalent to a peak FOM of 59.6 fJ/conversion-step.