A mid-texturing pixel rasterization pipeline architecture for 3D rendering processors | IEEE Conference Publication | IEEE Xplore

A mid-texturing pixel rasterization pipeline architecture for 3D rendering processors


Abstract:

As a 3D scene becomes increasingly complex and the screen resolution increases, the design of effective memory architecture is one of the most important issues for 3D ren...Show More

Abstract:

As a 3D scene becomes increasingly complex and the screen resolution increases, the design of effective memory architecture is one of the most important issues for 3D rendering processors. We propose a pixel rasterization architecture, which performs a depth test operation twice, before and after texture mapping. The proposed architecture eliminates memory bandwidth waste caused by fetching unnecessary obscured texture data, by performing the depth test before texture mapping. The proposed architecture reduces the miss penalties of the pixel cache by using a pre-fetch scheme - that is, a frame memory access, due to a cache miss at the first depth test, is done simultaneously with texture mapping. The proposed pixel rasterization architecture achieves memory bandwidth effectiveness and reduces power consumption, producing high-performance gains.
Date of Conference: 17-19 July 2002
Date Added to IEEE Xplore: 07 November 2002
Print ISBN:0-7695-1712-9
Print ISSN: 2160-0511
Conference Location: San Jose, CA, USA

References

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