Abstract:
Currently, television sets with flat plasma and LCD screens with improved resolutions and better color quality are emerging. To fully utilize their capabilities, lower re...Show MoreMetadata
Abstract:
Currently, television sets with flat plasma and LCD screens with improved resolutions and better color quality are emerging. To fully utilize their capabilities, lower resolution standard definition video material is enhanced. During such process, existing noise can become clearly visible, or additional artifacts may be introduced. These impairments are usually better visible in smooth image areas such as sky regions, motivating the development of special techniques for their removal. In this paper, we introduce a hardware accelerator for an existing pixel-accurate and spatially-consistent sky-detection algorithm. We describe the algorithmic and architectural design considerations of a resource-efficient real-time system, targeting an FPGA platform. Our results show that it is feasible to implement a simplified algorithm version by using only 5,756 logic-and 23,687 memory elements of the targeted device. A demonstrator setup using real-time camera signal, proves that images of up to 640times480 at a frame rate of 30 fps can be processed. Furthermore, according to our estimations, images with pixel rates up to 142 MHz, e.g. high definition TV, can be processed by the proposed system.
Published in: 2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP)
Date of Conference: 09-11 July 2007
Date Added to IEEE Xplore: 14 January 2008
ISBN Information:
Print ISSN: 1063-6862