Abstract:
This paper presents an area efficient decoder architecture that supports both perfectly structured and not perfectly structured LDPC codes. To verify our architecture, an...Show MoreMetadata
Abstract:
This paper presents an area efficient decoder architecture that supports both perfectly structured and not perfectly structured LDPC codes. To verify our architecture, an area-efficient LDPC decoder that supports both China Multimedia Mobile Broadcasting (CMMB) and Digital Terrestrial/ Television Multimedia Broadcasting (DTMB) standards is developed. A solution is proposed to avoid memory access conflict problem caused by TDMP algorithm. The main timing schedule is arranged carefully to handle the operations of our solution while avoiding much additional hardware consumption. We also optimize the extrinsic message storing strategy to reduce the memory bits needed. Besides the extrinsic message recover and the accumulate operation are merged together. Based on SMIC 0.13 um standard CMOS process, the core area of the decoder is only 4.75 mm2 and the maximum operating clock frequency is 200 MHz. With 5 iterations, the estimated average power consumption is 48.4 mW at 25 MHz for CMMB and 130.9 mW at 50 MHz for DTMB with 1.2V supply.
Published in: ASAP 2011 - 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors
Date of Conference: 11-14 September 2011
Date Added to IEEE Xplore: 13 October 2011
ISBN Information: